The present invention generally relates to fabricating nonvolatile memory devices. In particular, the present invention relates to improved methods of fabricating SONOS type nonvolatile memory devices.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), employ a memory cell characterized by a vertical stack of a tunnel oxide, a first polysilicon layer over the tunnel oxide, an ONO (oxide-nitride-oxide) interlevel dielectric over the first polysilicon layer, and a second polysilicon layer over the ONO interlevel dielectric. For example, Guterman et al (IEEE Transactions on Electron Devices, Vol. 26, No. 4, p. 576, 1979) relates to a floating gate nonvolatile memory cell consisting of a floating gate sandwiched between a gate oxide and an interlevel oxide, with a control gate over the interlevel oxide.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate xe2x80x9chotxe2x80x9d (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Subsequently, SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices have been introduced. See Chan et al, IEEE Electron Device Letters, Vol. 8, No. 3, p. 93, 1987. SONOS type flash memory cells are constructed having a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers). The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. Since the electrical charge is trapped locally near whichever side that is used as the drain, this structure can be described as a two-transistor cell, or two-bits per cell. If multi-level is used, then four or more bits per cell can be accomplished. Multi-bit cells enable SONOS type memory devices to have the advantage over others in facilitating the continuing trend increasing the amount of information held/processed on an integrated circuit chip.
For simplicity, a two-bit per cell implementation of SONOS is described. While both bits of SONOS type memory devices are programmed in a conventional manner, such as using hot electron programming, each bit is read in a direction opposite that in which it is programmed with a relatively low gate voltage. For example, the right bit is programmed conventionally by applying programming voltages to the gate and the drain while the source is grounded or at a lower voltage. Hot electrons are accelerated sufficiently so that they are injected into a region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it is written, meaning voltages are applied to the gate and the source while the drain is grounded or at a lower voltage. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming one of the bits leaves the other bit with its information intact and undisturbed. Programming one of the bits does, however, have a very small effect on the other bit. See Shimoji U.S. Pat. No. 5,349,221 and Hayes U.S. Pat. No. 4,173,766.
In Shimoji U.S. Pat. No. 5,349,221, when positive high voltages are respectively applied to the gate and the drain region of a SONOS type memory cell and the source region is grounded, hot electrons are produced in the boundary between the drain region and the channel. The hot electrons are locally injected into an insulation film and trapped therein. Consequently, information is written. At the time of reading out information, the drain region is grounded, a positive read voltage is applied to the source region, and a predetermined sense voltage is applied to the gate.
Reading in the reverse direction is most effective when relatively low gate voltages are used. A benefit of utilizing relatively low gate voltages in combination with reading in the reverse direction is that the potential drop across the portion of the channel beneath the trapped charge region is significantly reduced. A relatively small programming region or charge trapping region is possible due to the lower channel potential drop under the charge trapping region. This permits much faster programming times because the effect of the charge trapped in the localized trapping region is amplified. Programming times are reduced while the delta in threshold voltage between the programmed versus unprogrammed states remains the same as when the device is read in the forward direction.
SONOS type memory devices offer additional advantages as well. In particular, the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit. Another advantage includes reduced wearout from cycling thus increasing device longevity. An effect of reading in the reverse direction is that a much higher threshold voltage for the same amount of programming is possible. Thus, to achieve a sufficient delta in the threshold voltage between the programmed and unprogrammed states of the memory cell, a much smaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. Programming in the forward direction and reading in the reverse direction permits limiting the width of the charge trapping region to a narrow region near the drain (right bit) or the source. This allows for much more efficient erasing of the memory cell.
Another advantage of localized charge trapping is that during erase, the region of the nitride away from the drain does not experience deep depletion since the erase occurs near the drain only. The final threshold of the cell after erasing is self limited by the device structure itself. This is in direct contrast to conventional single transistor floating gate flash memory cells which often have deep depletion problems.
Although many advantages are described above, there are at least two disadvantages associated with SONOS type memory devices. One disadvantage is that isolation by LOCOS (LOCal Oxidation of Silicon) takes up a relatively large amount of space. Given the continuing trend towards miniaturization and increased integration of devices on an integrated circuit chip, efficient utilization of space is of increasing importance. Isolation by LOCOS also causes undesirable outgassing of dopants.
Another disadvantage with SONOS type memory devices is that LOCOS formation causes short channeling. There are high temperatures associated with LOCOS formation, often from 800xc2x0 C. to 1,100xc2x0 C. Short channeling is a decrease in the effective channel length, often represented as Leff. Unnecessarily decreasing the effective channel length results in an undesirably large current passing through the transistor at low gate voltages such as when the transistor is in the xe2x80x9coffxe2x80x9d state.
Thermal cycling associated with LOCOS formation also causes an increase in bitline to bitline punch-through leakage. That is, diffusion caused by thermal cycling leads to undesirable leakage between bitlines.
The SONOS type memory devices can be formed in the following manner. In Mitchell et al U.S. Pat. No. 5,168,334, EEPROM memory cells are formed with buried bitlines. The buried bitlines and bitline oxides are formed in the core region of the substrate prior to formation of the ONO dielectric. Alternatively, Mitchell et al forms EEPROM memory cells by forming an ONO dielectric, depositing polysilicon over the ONO dielectric, patterning the polysilicon, forming the buried bitlines, and removing the ONO dielectric covering the bitlines. In Eitan U.S. Pat. No. 5,966,603, an ONO dielectric is formed over the substrate, a bitline mask is patterned over the ONO dielectric in core while completely covering the periphery, portions of the top oxide and nitride layers left exposed by the bitline mask are etched/removed, the bitlines are implanted, then bitline oxides are formed over the bitlines. In Eitan PCT International Publication Number WO 99/60631, memory cells are formed by forming an ONO dielectric, a bitline mask with openings for the bitlines is formed over the ONO dielectric, the top oxide and nitride layers left exposed by the bitline mask are etched/removed, the bitlines are implanted, the bitline mask is removed, the exposed portions of the bottom oxide of the ONO dielectric are removed, gate oxides are grown including thick oxide growth over the bitlines, and polysilicon gates and wordlines are formed.
The present invention provides a simplified process for fabricating SONOS type nonvolatile memory devices, and in particular, a simplified process for forming buried bitlines in SONOS type nonvolatile memory devices. The SONOS type nonvolatile memory devices lead to the efficient production of dense, robust single-poly devices, having a substantially planar structure. Compared to conventional SONOS memory fabrication processes, the present invention eliminates the need for a core region etch step thus reducing costs and defect formation. The present invention eliminates high temperature thermal cycling associated with LOCOS formation in the core region, thereby minimizing and/or eliminating short channeling. The present invention also eliminates undesirable bird""s beak associated with LOCOS formation which may lead to fewer defects and/or improved scaling. Another advantage is that in some instances the bitline implant does not experience the periphery gate oxide thermal cycle.
One aspect of the present invention relates to a method of forming a nonvolatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
Another aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
Yet another aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; and forming gates in the core region and the periphery region.
Still yet another aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric having a first thickness in the periphery region; forming buried bitlines in the core region; increasing the thickness of the gate dielectric in at least a portion of the periphery region to provide a gate dielectric having a second thickness; and forming gates in the core region and the periphery region.